The present invention relates to the technology of semiconductor devices, and particularly to a semiconductor device which is suitable for an SDRAM (Synchronous Dynamic Random Access Memory) which can be switched to perform a SDR (Single Data Rate) operation and a DDR (Double Data Rate) operation
Synchronous memories such as SDRAMs have their operational timing controlled based on an external clock signal such as a system clock signal supplied from the outside. Synchronous memories of this type are characterized by relatively easy treatment of the internal operational timing by use of the external clock signal and the ability to achieve relatively fast operation.
SDRAMs are known which perform SDR type operations, in which data input/output is timed to the rising edge of the external clock signal, and DDR type operations, in which data input/output is timed to both the rising and falling edges of the external clock signal.
SDRAMs of the SDR type can operate relatively fast and can be used easily for general electronic systems which operate under control of a clock signal. Specifically, the relation between data input/output and the external clock signal, i.e., data input/output timed to the rising edge of the external clock signal, of the SDR-type SDRAM is fairly analogous to the operation of general electronic systems, in which operations are timed to the rising or falling edge or the transition from a low level to a high level (or from high to low) of the clock signal, or, in other words, it is analogous to the relation between the clock signal and the signal to be transferred in general electronic systems which operate by being timed to the leading edge or trailing edge of a clock signal.
In contrast, SDRAMs of the DDR type operate for data input/output by being timed to the rising and falling edges of a clock signal. Although DDR-type SDRAMs involve application electronic systems having some intricate timing design, these SDRAMs perform twice the data input/output operations per unit time as SDR-type SDRAMs at the same clock frequency. Namely, DDR-type SDRAMs are capable of faster data access.
SDRAMs of the SDR type and DDR type have similar characteristics such as the introduction of external control signals and command signals in synchronism with the external clock signal, the address input operation, and the data input/output operation, and have like circuit arrangements of the memory cell matrix and associated address selection circuit and the peripheral circuits such as the sense amplifiers and main amplifiers.
The inventors of the present invention have studied the design of a uniform semiconductor chip which can be employed both as an SDR-spec SDRAM and a DDR-spec SDRAM by switching. Accomplishing this semiconductor chip design enables the common use of photolithography masks for fabricating both SDR-spec and DDR-spec SDRAMs and the implementation of a common fabrication process and a common test process for both SDRAMS. As a result, the reduction of manufacturing cost can be expected.
Another expectation, which is derived from the configuration of any of the SDR-spec and DDR-spec SDRAMs embodied in a uniform semiconductor chip, is the potential capability to meet an increased demand of any type of SDRAMS.
In the course of the in-depth studies on the designing of SDR-spec and DDR-spec SDRAMs embodied in a uniform semiconductor chip, the inventors of the present invention have found the presence of the following problems to be solved.
(1) Problem on the Internal Clock System
It is necessary for the internal circuits of an SDRAM to be operative by being timed to both the rising edge and falling edge of the external clock signal so that the SDRAM can operate in the DDR mode. In this case, for controlling the internal circuits to operate in response to the rising and falling edges of the external clock signal, it is desired to generate an internal clock signal which is timed to both the rising and falling edges of the external clock signal, i.e., transitions from one level to another timed to the rising edge and falling edge of the external clock signal, so that the internal circuits operate in response to the rising and falling edges of the external clock signal.
Clock-based componential circuits, such as the input buffer, which operate in response to the external clock signal have inevitably a time lag or phase shift of the output signal relative to the input signal. Regardless of this inevitable output delay of componential circuits which base their operation on the external clock signal, it is desirable for the internal clock signal to have a reduced phase shift relative to the external clock signal. Another crucial design factor in the case of the relatively fast operation in the DDR mode is the generation of an internal clock signal in consideration of the operation delay of the internal circuits. It is desired to connect the semiconductor device to an external device such as a memory controller or microprocessor in a proper timing relation with the external clock signal regardless of the operation delay in the internal circuits. More desirable operation of the semiconductor device is made possible by providing an internal clock signal which has a leading phase relative to the external clock signal to a sufficient extent to compensate for the operation delay of the internal circuits. In order to produce an internal clock signal with a proper phase relation regardless of the operation delay and phase shift of the componential circuits, a clock regenerating circuit provided in the SDRAM for producing the internal clock signal from the external clock signal is designed to use the functions of signal phase judgement and adjustment, called DLL (delayed lock loop), PLL (phase-locked loop) and SMD (synchronous mirror delay), and to use the known circuit technique of signal phase control for producing a signal which is synchronized and phase-controlled to the input signal.
The clock-based circuit which produces an internal clock signal from the external clock signal for the device operation in SDR operation (or SDR mode or SDR specification) can conceivably be shared with the circuit for the DDR operation to achieve simplification of the whole uniform semiconductor chip. Nevertheless, these circuits are desirably separate from the clock-based circuit for the DDR operation under the following technical considerations.
Signals such as system clock signals produced in electronic systems are not necessarily designed to have a constant period and constant phase. Instead, it is even desirable for some electronic systems to have their clock period changed periodically. For example, in an electronic system operating based on a clock signal, a change of operation current of a clock-based circuit often produces a noise of a relatively large level. In case the clock period is changed periodically, noises attributable to the clock signal have their frequency spectrum dispersed by the alteration of the clock period, resulting in a reduced noise level at certain frequencies. For the effective dispersion of the noise frequency spectrum, it is desirable to change the clock period in a short interval, such as in every one or several clock cycles.
On the other hand, the above-mentioned circuit technique of signal phase control generally necessitates multiple clock cycles for phase control, and therefore it is not easily responsive to fast changing clock periods intended for the dispersion of the noise frequency spectrum. On this account, it should be a primary aim for the DDR mode to produce a fast clock signal from the external clock signal. In contrast, for the SDR mode, the internal clock signal virtually corresponds with the external clock signal, and it is desirably highly responsive to changing periods of the external clock signal.
Therefore, it is desirable to design separate clock-based circuits for the SDR mode and DDR mode.
(2) Problem on the Data Transfer Line
In the SDR-spec SDRAM, there are states in which read-out data and input data to be stored are processed simultaneously, whereas in the DDR-spec SDRAM, such states can be prevented.
In case a large number of data transfer lines are laid on a semiconductor chip so that it is adapted to both SDR and DDR modes simply, it will be necessary to provide an increased area for the layout of lines. This gives rise to problems of the chip cost and chip size.
(3) Problem on Data Input Timing Control
In the SDR-spec SDRAM, external data supply is enabled in the same clock cycle as that of the external command of a write operation, whereas in the DDR-spec SDRAM, external data supply is enabled in the clock cycle next to the clock cycle of the external command of a write operation. Accordingly, the SDR-spec SDRAM and DDR-spec SDRAM must receive input data to be stored at different timings of supply. Therefore, the data input circuit must have different operations for the SDR-spec SDRAM and DDR-spec SDRAM.
(4) Problem on Mask Register Control
In correspondence to the difference of the data input of writing between the SDR-spec SDRAM and DDR-spec SDRAM, it becomes necessary to have different control timings (data mask control timings) for validating or invalidating data supplied to the data input circuit depending on the type of SDRAM.
Based on the survey conducted after the present invention was made, the inventors of the present invention have found the presence of the following patent publications. The following comments concern the relationship between the present invention and these publications.
Japanese Patent Unexamined Publication No. Hei 10(1998)-302465 discloses a semiconductor memory device which is xe2x80x9cintended to improve the productivity and reduce the manufacturing cost based on the adoption of an option system which enables the selection of SDR mode and DDR modexe2x80x9d (quoted from paragraph number 0007). Specifically, the memory device is designed to include, at the location between a clock buffer for receiving an input clock signal and a pulse generator, a shift register which reverses its output signal level in response to the transition in one direction of the clock signal and a relay device, i.e., multiple inverters, which reverses its output signal level in response to the transition in both directions of the clock signal, with either the path of the shift register or the path of relay device being selected by the master signal of a mode selector. The mode selector which implements the switching based on the master signal has photo-mask switches or has NMOS transistors and fuses. A pulse generation circuit, which is made up of an inversion-delay means and logic means constituting an edge detecting circuit as a whole, produces a pulse signal in response to each of the rising edge and falling edge of the output signal from the shift register or the relay device
However, the pulse generation circuit described in the Patent Publication No. Hei 10(1998)-302465 is a relatively simple circuit made up of a delay circuit and logic circuit, and the publication does not disclose any innovative arrangement intended for high-speed operation based on the compensation of the delay characteristics of the PLL, DLL and SMD circuits that the present invention is concerned with. Accordingly, this publication does not reveal the above-mentioned problems pointed out by the inventors of the present invention.
Moreover, this Patent Publication No. Hei 10(1998)-302465 does not describe the signal switching scheme and line routing scheme to be considered for enabling the switching among multiple operation modes, as will be explained in detail later, besides the switching of internal clock signals.
It is an object of the present invention to provide a semiconductor device which is based on the innovative scheme of operation mode switching of a synchronous memory.
Another object of the present invention is to provide the technique of operation mode switching for SDRAMS.
Still another object of the present invention is to provide an innovative semiconductor device having multiple clock signal generation circuits with different operational characteristics for the input signal.
Still another object of the present invention is to provide a semiconductor device for an SDRAM having an operation mode switching ability which is responsive to changing clock signal periods.
Still another object of the present invention is to provide a semiconductor device for an SDRAM having an operation mode switching ability including operations with different data input timings.
Still another object of the present invention is to provide a semiconductor device which is operative in multiple modes and can have a relatively small line layout area.
Still another object of the present invention is to provide a line layout technique which enables signal transfer adapted to operation mode switching.
Still another object of the present invention is to provide a line layout technique suitable for signal transfer.
Still another object of the present invention is to provide an SDRAM design technique which enables the switching of specifications and the reduction of manufacturing cost.
These and other objects and novel features of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings.
Typical forms of the present invention are summarized as follows
(1) A semiconductor device includes a mode signal generation circuit which produces a mode selection signal, a first clock signal generation circuit (will also be called clock signal output circuit or clock regenerating circuit hereinafter) which has functions of signal phase judgement and adjustment and produces an output clock signal which is synchronized with an input clock signal and is phase-controlled, and a second clock signal generation circuit (will also be called clock signal output circuit hereinafter) which produces another output clock signal based on the buffering of the input clock signal.
In operation, when the selection signal from the selection signal generation circuit is in a first state, the output clock signal from the first clock signal generation circuit is validated. Consequently, the clock-based internal circuits in the semiconductor device operate in accordance with the timing of the output clock signal provided by the first clock signal generation circuit.
When the selection signal is in a second state which is different from the first state, the output clock signal from the second clock signal generation circuit is validated.
In a typical example, the semiconductor device is an SDRAM, and the selection signal operates to select the SDR-spec or DDR-spec. For example, the selection signal in the first state causes the semiconductor device to configure an SDR-spec SDRAM, and the data read-out operation, for example, takes place in synchronism with the output clock signal of the clock regenerating circuit.
Otherwise, the selection signal in the second state causes the semiconductor device to configure a DDR-spec SDRAM, and the data read-out operation takes place in synchronism with the output clock signal of the second clock signal generation circuit.
(2) A semiconductor device includes a selection signal generation circuit which produces a selection signal and a data line switching circuit which operates under control of the selection signal generation circuit.
In operation, if the selection signal from the selection signal generation circuit is in a first state, data lines made up of first and second data lines are set by the data line switching circuit to become unidirectional data lines which can implement one of data transfer from one circuit node to another circuit node and data transfer from the other circuit node to the one circuit node. Otherwise, if the selection signal is in a second state which is different from the first state, the first and second data lines are set to become bidirectional data lines which can implement both of data transfer from one circuit node to another circuit node and data transfer from the other circuit node to the one circuit node.
In a typical example, the semiconductor device is an SDRAM, and the selection signal operates to select the SDR-spec or DDR-spec, as in the case of the item (1)
Specifically, if the semiconductor device configures an SDR-spec SDRAM in response to the selection signal in the first state, the data lines become unidirectional data lines, with one data line being a writing data line and another data line being a read-out data line. In other words, the data lines are separated for the transfer of data for writing and for read-out. Consequently, the semiconductor device can deal with an internal situation of simultaneous data read-out and data writing.
Otherwise, if the semiconductor device configures a DDR-spec SDRAM in response to the selection signal in the second state, the data lines become bidirectional data lines which function as writing data lines or read-out data lines depending on the operational timing.
This data line switching scheme reduces the number of data transfer lines laid on the semiconductor chip even in the case of providing the ability of adaption to both SDR-spec and DDR-spec SDRAMs, whereby the chip area can be kept small.
(3) A semiconductor device includes a selection signal generation circuit which produces a selection signal and a timing control circuit which operates under control of the selection signal generation circuit. A data input circuit has its data input timing varied in steps of a multiple of the clock signal period.
In a typical example, the semiconductor device is an SDRAM, and the selection signal operates to select the SDR-spec or DDR-spec, as in the cases of the items (1) and (2).
In operation, if the semiconductor device configures an SDR-spec SDRAM in response to the selection signal in the first state, the data input circuit is controlled to place data, which has been received on the data terminal, on the data transfer line at a time point which is later by one clock period than the write command input.
Otherwise, if the selection signal is in the second state, the data input circuit is controlled to place data, which has been received on the data terminal, on the data transfer line at the time point which is later by two clock periods than the write command input.
In consequence, it is possible for the uniform semiconductor device which is operative as SDR-spec or DDR-spec SDRAMs to transfer input data to be stored to the data transfer line at the optimal timing adapted to the data input timing of each mode.
(4) A semiconductor device includes a selection signal generation circuit which produces a selection signal and a mask control circuit.
In operation, when the selection signal is in a first state, input data on the data terminal is taken into the data input circuit in response to the clock signal, and a first control signal is taken into the mask control circuit in response to the clock signal.
Otherwise, when the selection signal is in a second state, input data on the data terminal is taken into the data input circuit in response to a second control signal, and the first control signal is taken into the mask control circuit in response to the second control signal.
In consequence, it becomes possible for the semiconductor device to have different control timings (data mask control timings) for the validation or invalidation of data supplied to the data input circuit for the SDR-spec SDRAM and DDR-spec SDRAM so as to be compatible with the different write data inputs of the SDR-spec and DDR-spec SDRAMs.